FPGA Architecture and basic building blocks of FPGA

The architecture of FPGA consists of logic blocks, switch matrix and IO pad. The generic structure of the FPGA consists of three types of resources viz. configurable logic blocks, input/output blocks or pads, interconnection wires/switch matrix. Let us understand these basic building blocks of FPGA using block diagram with Xilinx example.

The most popular FPGA is Xilinx virtex-5 FPGA contains 6 input LUT associated with muxes,logic and flipflop as described below. The key building blocks and features of Virtex-5 FPGA are as follows.
• Each CLB (Configurable Logic Block) typically consists of multiple slices, each containing look-up tables (LUTs) to implement combinational logic, as well as flip-flops for storing sequential logic.
• Digital Clock Managers (DCMs) provide flexible clocking options.
• It houses on chip block RAM which can be used to implement data storage, FIFO buffers and other memory based functions.
• Some variants include embedded powerPC processor cores.
• It also contains high speed RocketIO transceivers that support serial communication protocols such as Gigabit ethernet, PCIe, serial RapidIO etc.
• SelectIO interface
• Embedded multiplier blocks
• External connectivity options for high speed serial interfaces, external memory (DDR, DDR2 etc.), general purpose IO pins.
• Supports various configuration modes including JTAG.

Modern FPGAs contain upto hundreds of thousands of CLBs. Sophisticated software such as Xilinx ISE and ModelSIM is used for development and to generate bitstream file for configuring FPGA.

The Basic FPGA Architecture has 2 dimensional arrays of logic blocks with a means for the user to configure the interconnection between the logic blocks and the function of each logic block. The FPGA Architecture consists of following building blocks of FPGA.

1. Configurable Logic Blocks (CLBs)

• CLBs are the fundamental FPGA building blocks and are responsible for implementing the combinational and sequential logic in the user's design.
• They typically consist of look-up tables (LUTs), multiplexers, flip-flops, and other logic elements that can be configured to implement a variety of logical functions.
Look Up Tables (LUTs) :
• LUTs are small memory units within CLBs that store pre-defined truth tables.
• They can be programmed to implement any Boolean logic function by configuring the input values and mapping them to the corresponding output values.
Logic Block consists of
LUT : It implements the combinational logic functions
Register (e.g. D flip flip): it stores the output of LUT
MUX : it is used for selection logic
N-bit LUT is implemented as a 2n X 1 memory; Inputs choose one of 2n memory locations. Memory locations are loaded with values taken from configuration bit streams of the user. Inputs to Mux control are the CLB inputs.

Flip-Flops and Registers :
• FPGAs contain a large number of flip-flops and registers that can be used to store and synchronize data within the design.
• These elements are crucial for implementing sequential logic and storing intermediate values during the operation of the circuit.
Clock Management : FPGAs often include dedicated clock management resources, such as PLLs (Phase-Locked Loops) and DLLs (Delay-Locked Loops), to generate and control clock signals within the design.
Block RAM (BRAM) and Distributed RAM : FPGAs include on-chip memory resources that can be configured as either block RAM or distributed RAM. Block RAMs are larger, dedicated memory blocks, while distributed RAM is spread across the CLBs.
Digital Signal Processing (DSP) Blocks : Many FPGAs include specialized DSP blocks that are optimized for performing arithmetic and logic operations, making them suitable for applications such as signal processing.
Configuration Memory : FPGAs store their configuration information in non-volatile memory, typically SRAM-based or flash memory. The configuration memory contains the bitstream that defines the logic and interconnection of the FPGA.

2. Interconnection Resources

• FPGAs have a mesh of programmable interconnects that allow signals to be routed between different logic elements. In other words, these Interconnects provide routing between the logic blocks to implements the user logic as per program.
• Switch matrices and programmable routing resources enable the configuration of connections between various CLBs and other components. Switch Matrix provides switching between interconnects depending on the logic.

3. Input/Output Blocks (IOBs)

• IOBs are responsible for interfacing with external devices and signals. In other words these Input/Output pads are used for outside world to communicate in Applications.
• They include programmable input buffers, output buffers, and bidirectional buffers to adapt to different voltage levels and drive external signals.

4. Configuration Interface

FPGAs have a configuration interface that allows users to load the bitstream and configure the device. This interface can be parallel or serial, depending on the FPGA model.

Adaptive LUTs

The basic building block of FPGA is the LUT(Look Up Table) based function generator. The number of inputs to LUT vary from three,four,six and even eight after experiments. Now we have adaptive LUTs which provides two outputs per single LUT with implementation of two function generators.

Types of FPGAs based on Applications

Based on applications FPGAs are categorized into three types high end FPGAs,low end FPGAs and Mid-range FPGAs. High end FPGAs are developed for high performance and logic density. Low end FPGAs are developed for low complexity,low power consumption per chip and low logic density. Mid range FPGAs are optical solution between the above two and developed as a balance between the cost and the performance.

Examples of High end FPGAs are Virtex family from Xilinx, Stratix family from Altera, ProASIC3 family by Microsemi, Speedster 22i family from Achronix.

Examples of low end FPGAs are Spartan family from Xilinx, Cyclone family from Altera,Mach XO/ICE40 from Lattice semiconductor, fusion family from Microsemi.

Examples of Mid range FPGAs are Artix-7/Kintex-7 series from Xlinix,Arria from Altera,ECP3 and ECP5 series from Lattice semiconductor and IGL002 from Microsemi.

Selecting an FPGA chip

Above mentioned internal architecture elements of FPGA are very important in selecting an FPGA chip based on the application. Important selection parameters are mentioned below.

• On chip RAM size
• Input/output interfaces
• Device speed grade
• Number of DSPs or Multiplier blocks
• Operating temperature
• Package size
• Device density
• Input/Output pins

Other than the above parameters the HDL code to be ported on the selected FPGA chip will decide whether the selected device is sufficient to store the logic for the application under development. The same can be inferred from the synthesis cycle count report.

Due to availability of advanced high end FPGAs, they have become alternative to ASIC and ASSP some vendors are marketing FPGAs suitable for testing the code before ASIC implementation. ARM based System On Chips(SoCs) combine processor,memory controllers and peripherals with custom FPGA in a single chip. Now FPGAs are available in 45nm,28nm,20nm and 16nm. Research is on going to develop 14 and 10nm devices soon.

Conclusion : Understanding the FPGA architecture and basic building blocks of FPGA are essential for effectively designing and implementing custom digital circuits using these versatile devices. Users program FPGAs using Hardware Description Languages (HDLs) like Verilog or VHDL, and the design is then synthesized and mapped to the architecture of FPGA using specialized tools provided by FPGA vendors such as Xilinx. Refer FPGA types >> for more on FPGA architectures and its types.

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